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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. dslvds1001 snls622 ? july 2018 dslvds1001 3.3-v lvds single channel high speed differential driver 1 1 features 1 ? designed for signaling rates up to 400-mbps ? single 3.3-v power supply (3.0-v to 3.6-v range) ? 700-ps (100-ps typical) maximum differential skew ? 1.5-ns maximum propagation delay ? drives small swing ( 350-mv) differential signal levels ? power off protection (outputs in tri-state) ? flow-through pinout simplifies pcb layout ? low power dissipation (23-mw @ 3.3-v typical) ? sot-23 5-lead package ? meets or exceeds ansi tia/eia-644-a standard ? industrial temperature operating range (-40 c to +85 c) 2 applications ? board to board communication ? test and measurement ? motor drive ? wireless infrastructure ? telecom infrastructure ? printer ? multi function printer ? professional video cameras ? enterprise and cinema projectors ? led video wall ? nic card ? rack server ? ultrasound scanners 3 description the dslvds1001 is a single channel low voltage differential signaling (lvds) driver device designed for applications requiring low power dissipation, low noise, and high data rates. in addition, the short circuit fault current is also minimized. the device is designed to support data rates that are up to 400- mbps (200-mhz) utilizing lvds technology. the dslvds1001 accepts a 3.3-v lvcmos/lvttl input level and outputs low voltage ( 350 mv typical) differential signals that have low electromagnetic interference (emi). the device is in a 5-lead sot-23 package that is designed for easy pcb layout. the dslvds1001 can be paired with its companion single line receiver, the dslvds1002, or with any lvds receiver, to provide a high-speed lvds interface. device information (1) part number package body size (nom) dslvds1001 sot-23 dbv 3.00 mm x 3.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. functional diagram typical application lvcmos/lvtll in out + out - ep blue receiver driver 100 lvcmos/lvttl in out + out - vcc gnd dslvds1001 dslvds1002 advance information technical documents support &community ordernow productfolder tools & software
2 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings ............................................................ 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 4 6.6 switching characteristics .......................................... 5 7 parameter measurement information .................. 6 8 detailed description .............................................. 7 8.1 overview ................................................................... 7 8.2 functional block diagram ......................................... 7 8.3 feature description ................................................... 7 8.4 device functional modes .......................................... 8 9 application and implementation .......................... 9 9.1 application information .............................................. 9 9.2 typical application .................................................... 9 10 power supply recommendations ..................... 13 10.1 power supply considerations ............................... 13 11 layout ................................................................... 14 11.1 layout guidelines ................................................. 14 11.2 layout example .................................................... 17 12 device and documentation support ................. 18 12.1 receiving notification of documentation updates 18 12.2 community resources .......................................... 18 12.3 trademarks ........................................................... 18 12.4 electrostatic discharge caution ............................ 18 12.5 glossary ................................................................ 18 13 mechanical, packaging, and orderable information ........................................................... 19 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes july 2018 * initial release. advance information
3 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions dvb package 5-pin sot-23 top view package pin number pin name description sot-23 1 v dd power supply pin, +3.3v 0.3v 2 gnd ground pin 3 out ? inverting driver output pin 4 out+ non-inverting driver output pin 5 lvcmos/lvttl in lvcmos/lvttl driver input pin advance information
4 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage v dd ? 0.3 4 v lvcmos input voltage (ttl in) ? 0.3 3.6 v lvds output voltage (out ) ? 0.3 3.9 v lvds output short circuit current 24 ma lead temperature ? soldering 260 c maximum junction temperature 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. pins listed as 9000 v may actually have higher performance. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. pins listed as 2000 v may actually have higher performance. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 9000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 2000 6.3 recommended operating conditions min typ max units supply voltage (v dd ) 3.0 3.3 3.6 v temperature (t a ) -40 +25 +85 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) dslvds1001 unit sot-23 (dbv) 5 pins r ja junction-to-ambient thermal resistance 179.4 c/w r jc(top) junction-to-case (top) thermal resistance 88.7 c/w r jb junction-to-board thermal resistance 36.2 c/w jt junction-to-top characterization parameter 4.6 c/w jb junction-to-board characterization parameter 35.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w (1) current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenced to ground except v od . (2) all typicals are given for: v dd = +3.3v and t a = +25 c. 6.5 electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) parameter test conditions min typ max unit |v od | output differential voltage r l = 100 ( figure 2 and figure 3 ) out+, out ? pins 250 350 450 mv advance information
5 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) parameter test conditions min typ max unit (3) output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. v od v od magnitude change r l = 100 ( figure 2 and figure 3 ) out+, out ? pins 3 35 mv v os offset voltage r l = 100 ( figure 2 ) out+, out ? pins 1.125 1.25 1.375 v v os offset magnitude change r l = 100 ( figure 2 ) out+, out ? pins 25 mv i off power-off leakage v out = 3.6 v or gnd, v dd = 0 v out+, out ? pins 2 15 a i os output short circuit current (3) v out+ and v out ? = 0 v out+, out ? pins ? 5 ? 20 ma i osd differential output short circuit current (3) v od = 0 v out+, out ? pins ? 5 ? 12 ma v ih input high voltage ttl in pin 2.0 v dd v v il input low voltage ttl in pin gnd 0.8 v i ih input high current v in = 3.3 v or 2.4 v ttl in pin 2 15 a i il input low current v in = gnd or 0.5 v ttl in pin 2 15 a v cl input clamp voltage i cl = ? 18 ma ttl in pin ? 1.5 ? 0.6 v c in input capacitance ttl in pin 3 pf i dd power supply current no load v in = v dd or gnd 5 8 ma r l = 100 v in = v dd or gnd 7 10 (1) all typicals are given for: v dd = +3.3v and t a = +25 c. (2) these parameters are specified by design. the limits are based on statistical analysis of the device performance over pvt (process, voltage, temperature) ranges. (3) c l includes probe and fixture capacitance. (4) generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50 , t r 1 ns, t f 1 ns (10%-90%). (5) t skd1 , |t phld ? t plhd |, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. (6) t skd4 , part to part skew, is the differential channel to channel skew of any event between devices. this specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t skd4 is defined as |max ? min| differential propagation delay. (7) f max generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, 0v to 3v. output criteria: duty cycle = 45%/55%, v od > 250mv. the parameter is specified by design. the limit is based on the statistical analysis of the device over the pvt range by the transitions times (t tlh and t thl ). 6.6 switching characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) (3) (4) parameter test conditions min typ max units t phld differential propagation delay high to low r l = 100 , c l = 15 pf 0.5 1.0 1.5 ns t plhd differential propagation delay low to high ( figure 4 and figure 5 ) 0.5 1.1 1.5 ns t skd1 differential pulse skew |t phld ? t plhd | (5) 0 0.1 0.7 ns t skd4 differential part to part skew (6) 0 0.4 1.2 ns t r rise time 0.2 0.5 1.0 ns t f fall time 0.2 0.5 1.0 ns f max maximum operating frequency (7) 200 250 mhz advance information
6 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information figure 2. differential driver dc test circuit figure 3. differential driver full load dc test circuit figure 4. differential driver propagation delay and transition time test circuit figure 5. differential driver propagation delay and transition time waveforms advance information
7 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the dslvds1001 device is a single-channel, low-voltage differential signaling (lvds) line driver. it operates from a single supply that is nominally 3.3 v, but can be as low as 3.0 v and as high as 3.6 v. the input signal to the dslvds1001 is an lvcmos/lvttl signal. the output of the device is a differential signal complying with the lvds standard (tia/eia-644). the differential output signal operates with a signal level of 340 mv, nominally, at a common-mode voltage of 1.2 v. this low differential output voltage results in a low emitted radiated energy, which is dependent on the signal slew rate. the differential nature of the output provides immunity to common-mode coupled signals that the driven signal may experience. the dslvds1001 device is intended to drive a 100- transmission line. this transmission line may be a printed-circuit board (pcb) or cabled interconnect. with transmission lines, the optimum signal quality and power delivery is reached when the transmission line is terminated with a load equal to the characteristic impedance of the interconnect. likewise, the driven 100- transmission line should be terminated with a matched resistance. 8.2 functional block diagram 8.3 feature description 8.3.1 driver output voltage and power-on reset the dslvds1001 driver operates and meets all the specified performance requirements for supply voltages in the range of 3.0 v to 3.6 v. when the supply voltage drops below 1.5 v (or is turning on and has not yet reached 1.5 v), power-on reset circuitry set the driver output to a high-impedance state. 8.3.2 driver offset an lvds-compliant driver is required to maintain the common-mode output voltage at 1.2 v ( 75 mv). the dslvds1001 incorporates sense circuitry and a control loop to source common-mode current and keep the output signal within specified values. further, the device maintains the output common-mode voltage at this set point over the full 3.0-v to 3.6-v supply range. lvcmos/lvtll in out + out - advance information
8 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4 device functional modes 8.4.1 dslvds1001 truth table as can be seen in table 1 , when the driver input is left open, the differential output will be driven low. table 1. driver function input outputs lvcmos/lvttl in out + out - h h l l l h open ? ? advance information
9 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the dslvds1001 device is a single-channel lvds driver. the functionality of this device is simple, yet extremely flexible, leading to its use in designs ranging from wireless base stations to desktop computers. the varied class of potential applications share features and applications discussed in the paragraphs below. 9.2 typical application 9.2.1 point-to-point communications the most basic application for lvds buffers, as found in this data sheet, is for point-to-point communications of digital data, as shown in figure 6 . figure 6. typical application a point-to-point communications channel has a single transmitter (driver) and a single receiver. this communications topology is often referred to as simplex. in figure 6 the driver receives a single-ended input signal and the receiver outputs a single-ended recovered signal. the lvds driver converts the single-ended input to a differential signal for transmission over a balanced interconnecting media of 100- characteristic impedance. the conversion from a single-ended signal to an lvds signal retains the digital data payload while translating to a signal whose features are more appropriate for communication over extended distances or in a noisy environment. 9.2.2 design requirements design parameters example value driver supply voltage (v cc ) 3.0 to 3.6 v driver input voltage 0 to 3.6 v driver signaling rate dc to 400 mbps interconnect characteristic impedance 100 termination resistance 100 number of receiver nodes 1 ground shift between driver and receiver 1 v ep blue receiver driver 100 lvcmos/lvttl in out + out - vcc gnd dslvds1001 dslvds1002 advance information
10 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. 9.2.3 detailed design procedure 9.2.3.1 driver supply voltage the dslvds1001 driver is operated from a single supply. the device can support operation with a supply as low as 3.0 v and as high as 3.6 v. the driver output voltage is dependent upon the chosen supply voltage. the minimum output voltage stays within the specified lvds limits (247 mv to 450 mv) for a 3.3-v supply. if the supply range is between 3.0 v and 3.6 v, the minimum output voltage may be as low as 150 mv. if a communication link is designed to operate with a supply within this lower range, the channel noise margin will need to be looked at carefully to ensure error-free operation. 9.2.3.2 driver bypass capacitance bypass capacitors play a key role in power distribution circuitry. specifically, they create low-impedance paths between power and ground. at low frequencies, a good digital power supply offers very low-impedance paths between its terminals. however, as higher frequency currents propagate through power traces, the source is quite often incapable of maintaining a low-impedance path to ground. bypass capacitors are used to address this shortcoming. usually, large bypass capacitors (10 f to 1000 f) at the board-level do a good job up into the khz range. due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. to solve this problem, one must resort to the use of smaller capacitors (nf to f range) installed locally next to the integrated circuit. multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nh. for comparison purposes, a typical capacitor with leads has a lead inductance around 5 nh. the value of the bypass capacitors used locally with lvds chips can be determined by the following formula according to johnson (1) , equations 8.18 to 8.21. a conservative rise time of 200 ps and a worst-case change in supply current of 1 a covers the whole range of lvds devices offered by texas instruments. in this example, the maximum power supply noise tolerated is 200 mv; however, this figure varies depending on the noise budget available in your design. (1) (1) (2) the following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor ( > 10 f) and the value of capacitance found above (0.001 f). you should place the smallest value of capacitance as close as possible to the chip. figure 7. recommended lvds bypass capacitor layout lvds 1a c 200 ps 0.001 f 0.2v ? ? = = m ? ? maximum step change supply current chip rise time maximum power supply noise i c t v d ? ? = ? d ? advance information 0.1 f 0.001 f 3.3 v
11 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.3.3 driver input voltage the dslvds1001 input is designed to support a wide input voltage range. the input stage can accept signals as high as 3.6 v. 9.2.3.4 driver output voltage the dslvds1001 driver output is a 1.2-v common-mode voltage, with a nominal differential output signal of 350 mv. this 350 mv is the absolute value of the differential swing (v od = |v + ? v ? |). the peak-to-peak differential voltage is twice this value, or 700 mv. as we will see shortly, lvds receiver thresholds are 100 mv. with these receiver decision thresholds, it is clear that the disadvantage of operating the driver with a lower supply will be noise margin. with fully compliant lvds drivers and receivers, we would expect a minimum of ~150 mv of noise margin (247-mv minimum output voltage ? 100-mv maximum input requirement). if we operate the dslvds1001 with a supply in the range of 3.0 v to 3.6 v, the minimum noise margin will drop to 150 mv. 9.2.3.5 interconnecting media the physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the lvds standard, the key points which will be included here. this media may be a twisted pair, twinax, flat ribbon cable, or pcb traces. the nominal characteristic impedance of the interconnect should be between 100 and 120 with variation no more than 10% (90 to 132 ). 9.2.3.6 pcb transmission lines as per snla187 , figure 8 depicts several transmission line structures commonly used in printed-circuit boards (pcbs). each structure consists of a signal line and a return path with uniform cross-section along its length. a microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. a stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. the dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmission line). when two signal lines are placed close by, they form a pair of coupled transmission lines. figure 8 shows examples of edge-coupled microstrip lines, and edge-coupled or broad-side-coupled striplines. when excited by differential signals, the coupled transmission line is referred to as a differential pair. the characteristic impedance of each line is called odd-mode impedance. the sum of the odd-mode impedances of each line is the differential impedance of the differential pair. in addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. when the two lines are immediately adjacent; for example, s is less than 2w, the differential pair is called a tightly- coupled differential pair. to maintain constant differential impedance along the length, it is important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines. advance information
12 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 8. controlled-impedance transmission lines 9.2.3.7 termination resistor as shown earlier, an lvds communication channel employs a current source driving a transmission line which is terminated with a resistive load. this load serves to convert the transmitted current into a voltage at the receiver input. to ensure incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination resistance should be matched to the characteristic impedance of the transmission line. the designer should ensure that the termination resistance is within 10% of the nominal media characteristic impedance. if the transmission line is targeted for 100- impedance, the termination resistance should be between 90 and 110 . the line termination resistance should be located as close as possible to the receiver, thereby minimizing the stub length from the resistor to the receiver. while we talk in this section about point-to-point communications, a word of caution is useful when a multidrop topology is used. in such topologies, line termination resistors are to be located only at the end(s) of the transmission line. 0 r 87 5.98 h z ln 0.8 w t 1.41 ? h ? 1 > @ > @ 0 r 1.9 2 h t 60 z ln 0.8 w t ? ? h ? 1 s 0.96 h diff 0 z 2 z 1 0.48 e u ? u u u ? ? 1 s 2.9 h diff 0 z 2 z 1 0.347e u ? u u ? ? 1 co-planar coupled microstrips broad-side coupled striplines edge-coupled edge-coupled single-ended microstrip single-ended stripline w h t w t h h s h differential microstrip differential stripline s h s h h g g w w w s advance information
13 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations 10.1 power supply considerations the dslvds1001 driver is designed to operate from a single power supply with supply voltage in the range of 3.0 v to 3.6 v. in a typical application, a driver and a receiver may be on separate boards, or even separate equipment. in these cases, separate supplies would be used at each location. the expected ground potential difference between the driver power supply and the receiver power supply would be less than | 1 v|. board level and local device level bypass capacitance should be used. advance information
14 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated (2) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. (3) mark i. montrose. 1996. printed circuit board design techniques for emc compliance. ieee press. isbn number 0780311310. (4) clyde f. coombs, jr. ed, printed circuits handbook, mcgraw hill, isbn number 0070127549. 11 layout 11.1 layout guidelines 11.1.1 layout guidelines 11.1.1.1 microstrip vs. stripline topologies as per slld009 , printed-circuit boards usually offer designers two transmission line options: microstrip and stripline. microstrips are traces on the outer layer of a pcb, as shown in figure 9 . figure 9. microstrip topology on the other hand, striplines are traces between two ground planes. striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. however, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. ti recommends routing lvds signals on microstrip transmission lines, if possible. the pcb traces allow designers to specify the necessary tolerances for z o based on the overall noise budget and reflection allowances. footnotes 1 (2) , 2 (3) , and 3 (4) provide formulas for z o and t pd for differential and single-ended traces. (2) (3) (4) figure 10. stripline topology 11.1.1.2 dielectric type and board construction the speeds at which signals travel across the board dictates the choice of dielectric. fr-4, or equivalent, usually provides adequate performance for use with lvds signals. if rise or fall times of lvcmos/lvttl signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as rogers ? 4350 or nelco n4000-13 is better suited. once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. the following set of guidelines were developed experimentally through several designs involving lvds devices: ? copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz ? all exposed circuitry should be solder-plated (60/40) to 7.62 m or 0.0003 in (minimum). ? copper plating should be 25.4 m or 0.001 in (minimum) in plated-through-holes. ? solder mask over bare copper with solder hot-air leveling advance information
15 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) 11.1.1.3 recommended stack layout following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. to reduce the lvcmos/lvttl to lvds crosstalk, it is a good practice to have at least two separate signal planes as shown in figure 11 . figure 11. four-layer pcb board note the separation between layers 2 and 3 should be 127 m (0.005 in). by keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. one of the most common stack configurations is the six-layer board, as shown in figure 12 . figure 12. six-layer pcb board in this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. the result is improved signal integrity; however, fabrication is more expensive. using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6. 11.1.1.4 separation between traces the separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. low noise coupling requires close coupling between the differential pair of an lvds link to benefit from the electromagnetic field cancellation. the traces should be 100- ? differential and thus coupled in the manner that best fits this requirement. in addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. in the case of two adjacent single-ended traces, one should use the 3-w rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. this increased separation effectively reduces the potential for crosstalk. the same rule should be applied to the separation between adjacent lvds differential pairs, whether the traces are edge-coupled or broad-side-coupled. figure 13. 3-w rule for single-ended and differential traces (top view) layer 4: routed plane (ttl signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (lvds signals) layer 4: ground plane layer 5: ground plane layer 4: routed plane (ttl/cmos signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (lvds signals) t 2 w w ww minimum spacing as defined by pcb vendor lvds pair ttl/cmos trace differential traces single-ended traces s = advance information
16 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) you should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. for instance, it is best to avoid sharp 90 turns to prevent discontinuities in the signal path. using successive 45 turns tends to minimize reflections. 11.1.1.5 crosstalk and ground bounce minimization to reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. a ground plane usually achieves this. because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. lowering the area of the current loop lowers the potential for crosstalk. traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. discontinuities in the ground plane increase the return path inductance and should be avoided. 11.1.1.6 decoupling each power or ground lead of a high-speed device should be connected to the pcb through a low inductance path. for best results, one or more vias are used to connect a power or ground pin to the nearby plane. ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. placing a power plane closer to the top of the board reduces the effective via length and its associated inductance. figure 14. low inductance, high-capacitance power connection bypass capacitors should be placed close to v dd pins. they can be placed conveniently near the corners or underneath the package to minimize the loop area. this extends the useful frequency range of the added capacitance. small-physical-size capacitors, such as 0402 or even 0201, or x7r surface-mount capacitors should be used to minimize body inductance of capacitors. each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor as shown in figure 15 (a). an x7r surface-mount capacitor of size 0402 has about 0.5 nh of body inductance. at frequencies above 30 mhz or so, x7r capacitors behave as low-impedance inductors. to extend the operating frequency range to a few hundred mhz, an array of different capacitor values like 100 pf, 1 nf, 0.03 f, and 0.1 f are commonly used in parallel. the most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. with a 2-mil fr4 dielectric, there is approximately 500 pf per square inch of pcb. refer back to figure 5-1 for some examples. many high-speed devices provide a low-inductance gnd connection on the backside of the package. this center dap must be connected to a ground plane through an array of vias. the via array reduces the effective inductance to ground and enhances the thermal performance of the small surface mount technology (smt) package. placing vias around the perimeter of the dap connection ensures proper heat spreading and the lowest possible die temperature. placing high-performance devices on opposing sides of the pcb using two gnd planes (as shown in figure 8 ) creates multiple paths for heat transfer. often thermal pcb issues are the result of one device adding heat to another, resulting in a very high local temperature. multiple paths for heat transfer minimize this possibility. in many cases the gnd dap that is so advance information board thickness approximately 100 mil 2 mil typical 12-layer pcb 4 mil 4 mil 6 mil 6 mil v cc via gnd via top signal layer + gnd fill v dd 1 plane gnd plane signal layer buried capacitor > signal layer gnd plane v dd 2 plane bottom signal layer + gnd fill buried capacitor > gnd plane signal layers v cc plane
17 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad- to-dap spacing as shown in figure 15 (b). when this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum. it is important to place the v dd via as close to the device pin as possible while still allowing for sufficient solder mask coverage. if the via is left open, solder may flow from the pad and into the via barrel. this will result in a poor solder connection. figure 15. typical decoupling capacitor layouts 11.2 layout example at least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. increase the spacing between signal paths for long parallel runs to reduce crosstalk. boards with limited real estate can benefit from the staggered trace layout, as shown in figure 16 . figure 16. staggered trace layout this configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. to ensure continuity in the ground signal path, ti recommends having an adjacent ground via for every signal via, as shown in figure 17 . note that vias create additional capacitance. for example, a typical via has a lumped capacitance effect of 1/2 pf to 1 pf in fr4. figure 17. ground via location (side view) short and low-impedance connection of the device ground pins to the pcb ground plane reduces ground bounce. holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. to minimize emi problems, ti recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. advance information 0402 0402 v dd in in+ (a) (b) layer 6 layer 1 signal trace uninterrupted ground plane signal trace uninterrupted ground plane signal via ground via
18 dslvds1001 snls622 ? july 2018 www.ti.com product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. rogers is a trademark of rogers corporation. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. advance information
19 dslvds1001 www.ti.com snls622 ? july 2018 product folder links: dslvds1001 submit documentation feedback copyright ? 2018, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 24-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dslvds1001dbvr preview sot-23 dbv 5 1000 tbd call ti call ti -40 to 85 dslvds1001dbvt preview sot-23 dbv 5 250 tbd call ti call ti -40 to 85 pdslvds1001dbvt active sot-23 dbv 5 1000 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2
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